Design and Post-Layout Evaluation of a Source-Follower-Buffered CMOS LDO Regulator

Abstract

Abstract

This paper presents the implementation and post-layout evaluation of a source-follower-buffered CMOS low-dropout regulator in a 0.18 μm process. The design combines an error amplifier, a cascode bandgap reference, a source-follower buffer, a PMOS pass device, and resistive feedback. The extracted RC evaluation uses an ideal 4.7 μF output capacitor. At the typical process corner, 27 °C, and a 3.0 V input, the simulated output decreases from 1.80446 V to 1.79236 V as the load increases from 0 to 500 mA, corresponding to a load-regulation magnitude of approximately 0.02420 mV/mA. A post-layout STB sweep at 11 loads and three process corners gives a minimum defined sampled phase margin of 21.04° at SS and 150 mA. At SS and 500 mA, the DC output drops to approximately 1.646 V and the loop gain has no 0 dB crossing, so conventional phase and gain margins are undefined. At 300 mA, the integrated output noise is 1.339 mVrms over 1 Hz–100 MHz, with the bandgap reference accounting for 95.68% of the simulated integrated noise power. The results reveal load-dependent stability and regulation limitations; the 500 mA nominal-corner result is not a process-independent rating. Silicon measurements and comprehensive statistical and physical-reliability verification remain outside the demonstrated scope.