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This work proposed a novel cell-level erase scheme called Hole Pool (HP) erase by integrating the Cell-level Voltage (CV) scheme with the Source Acceptor Doping (SAD) structure, demonstrating its feasibility and applicability to highly stacked architectures.
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Abstract With advances in AI and the widespread adoption of NAND Flash technology imposing increasingly stringent performance requirements, conventional erase was unable to provide precise erasing in NAND Flash storage systems. This work proposed a novel cell-level erase scheme called Hole Pool (HP) erase by integrating the Cell-level Voltage (CV) scheme with the Source Acceptor Doping (SAD) structure. The technique was evaluated in 3D NAND Flash structures with different numbers of layers, in which stable electric field and charge variation characteristics were obtained, thereby demonstrating its feasibility and applicability to highly stacked architectures. The results demonstrated that the HP erase enabled precise cell-level erase and provided a viable solution for the future development of erase technology, advancing NAND Flash memory technology.
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@article{liang2026Novel,
title = {Novel cell-level erase for 3D NAND Flash memory},
author = {nanchang liang and Zhicheng Liu and Guokun Ma and Wu ShiWen and Liu X and Lin Lv and Siyuan Li and Hao Wang},
journal = {Semiconductor Science and Technology},
year = {2026},
doi = {10.1088/1361-6641/ae8f6e},
url = {https://doi.org/10.1088/1361-6641/ae8f6e}
}
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