Design of Event-Triggered PI–P Controller for Discrete-Time Cascade Control Systems with Time-Varying Delay

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Time-varying delay and limited communication resources pose two fundamental challenges to the stability and efficiency of discrete-time cascade control systems (CCS). To address these issues, this paper presents, for the first time, the co-design of an event-triggered PI–P controller for discrete-time CCS with time-varying delay. A discrete-time state-space model with time-varying state delay is first established to accurately characterize the cascade dynamics. An event-triggered mechanism (ETM) is then introduced to effectively reduce redundant data transmissions while maintaining desired control performance. Based on Lyapunov stability theory, sufficient conditions are derived to enable the joint synthesis of the primary Proportional (P) controller, the secondary Proportional–Integral (PI) controller, and the event-triggering thresholds in an integrated manner. Simulation results confirm that the proposed method delivers improved transient performance and steady-state accuracy while reducing control update frequency, thereby providing a superior balance between control performance and communication efficiency compared with conventional event-triggered P–P cascade control strategies. Overall, the proposed co-design framework offers an effective and systematic solution for both enhancing stability and reducing unnecessary control updates in discrete-time CCS subject to time-varying delay.