Graph Theory and Algorithms Open access Peer reviewed

DCSR-GCN: A High-Performance GCN Accelerator Based on Dynamic Compression and Sparsity Reordering

Junsheng Chang, Yimin Zhao, Yuxin Huang, Sheng Liu and 1 more

ACM Transactions on Design Automation of Electronic Systems | Sep 24, 2026

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DCSR-GCN, a high-performance GCN accelerator based on dynamic compression and sparsity reordering based on dynamic compression and sparsity reordering, is presented and a two-phase reordering algorithm that combines conflict-aware row scheduling with reuse-aware column grouping is proposed, thereby mitigating RAW conflicts and improving memory access efficiency is proposed.

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Graph Convolutional Networks (GCNs) are widely used in tasks involving irregular graph data, such as recommendation. The hybrid execution pattern of sparse aggregation and dense combination during inference limits the efficiency of general processors like CPU and GPU. Therefore, designing dedicated accelerators for GCN inference has become an important research direction. However, existing GCN accelerators still suffer from high storage overhead caused by sparse indices and frequent read-after-write (RAW) conflicts during the aggregation phase, which limit system throughput and energy efficiency. To address these challenges, we adopt the hardware-software co-design approach and present DCSR-GCN, a high-performance GCN accelerator based on dynamic compression and sparsity reordering. First, we design an Enhanced Compressed Sparse Row (ECSR) format to reduce adjacency index storage space, and directly embed node degree fields to eliminate redundant computations in aggregation. Second, we propose a two-phase reordering algorithm that combines conflict-aware row scheduling with reuse-aware column grouping, thereby mitigating RAW conflicts and improving memory access efficiency. Finally, to fully exploit the benefits of sparse optimizations, we design a high-throughput vector systolic array that accelerates feature transformation in combination. Evaluations show that DCSR-GCN achieves up to 26.03 ×, 4.19 ×, and 3.52 × speedup compared to HyGCN, GCNAX, and MEGA, respectively.

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Junsheng Chang

first | National University of Defense Technology | ORCID 0009-0006-3061-980X

Yimin Zhao

middle | National University of Defense Technology | ORCID 0009-0003-3683-4584

Yuxin Huang

middle | National University of Defense Technology | ORCID 0009-0001-6966-1195

Sheng Liu

middle | National University of Defense Technology | ORCID 0009-0005-1413-0070

Li Shen

last | National University of Defense Technology | ORCID 0000-0001-9043-2998

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@article{Chang2026DCSR,
  title = {DCSR-GCN: A High-Performance GCN Accelerator Based on Dynamic Compression and Sparsity Reordering},
  author = {Junsheng Chang and Yimin Zhao and Yuxin Huang and Sheng Liu and Li Shen},
  journal = {ACM Transactions on Design Automation of Electronic Systems},
  year = {2026},
  doi = {10.1145/3838804},
  url = {https://doi.org/10.1145/3838804}
}

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