Analog and Mixed-Signal Circuit Design Open access Peer reviewed

A 10‐Bit 400‐MS/s Subrange SAR ADC With Binary‐Scaled Recombination Capacitive DAC in 28‐nm CMOS

Yuzhen Zhang, Xuan Guo, Hanbo Jia, Li Luo and 1 more

International Journal of Circuit Theory and Applications | Oct 26, 2026

Abstract

ABSTRACT This paper presents a 10‐bit 400‐MS/s subrange successive approximation register (SAR) analog‐to‐digital converter (ADC) designed in a 28‐nm process. To mitigate the gain errors inherent in the subrange SAR architecture, a binary‐scaled recombination redundancy algorithm is adopted. In addition, a detect‐and‐skip algorithm is designed to further enhance the conversion efficiency. An improved low‐noise comparator topology is also introduced. By adding an extra transistor, the variation of parasitic capacitance at the comparator input nodes during the ADC sampling phase is suppressed, which improves the ADC linearity. To validate the effectiveness, an ADC schematic is designed and simulated. The simulation results show that the ADC achieves a 61.95‐dB SFDR and 53.67‐dB SNDR at 196.9‐MHz input frequency.

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Authors

Researchers on this paper

Yuzhen Zhang

first | Beijing Jiaotong University | ORCID 0000-0003-1231-3074

Xuan Guo

middle | Chinese Academy of Sciences | ORCID 0000-0001-8052-6165

Hanbo Jia

middle | Chinese Academy of Sciences | ORCID 0000-0002-8719-5757

Li Luo

middle | Beijing Jiaotong University

Xinyu Liu

last | Chinese Academy of Sciences

Research areas

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Advancements in PLL and VCO Technologies Radio Frequency Integrated Circuit Design Latest Analog and Mixed-Signal Circuit Design research

Citation

BibTeX

@article{Zhang2026Subrange,
  title = {A 10‐Bit 400‐MS/s Subrange SAR ADC With Binary‐Scaled Recombination Capacitive DAC in 28‐nm CMOS},
  author = {Yuzhen Zhang and Xuan Guo and Hanbo Jia and Li Luo and Xinyu Liu},
  journal = {International Journal of Circuit Theory and Applications},
  year = {2026},
  doi = {10.1002/cta.70684},
  url = {https://doi.org/10.1002/cta.70684}
}

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