A 0.61 ppm/℃ PMOS-Only Temperature Compensated Voltage Reference for Battery Management System

Abstract

Abstract

Accurate cell-voltage monitoring in battery management systems (BMS) requires a reference voltage whose temperature drift is well below the 1 mV measurement target. This paper presents a PMOS-only stacked, triode-region voltage reference architecture that combines complementary-to-absolute-temperature (CTAT) current behavior in the weak-triode region with proportional-to-absolute-temperature (PTAT) current behavior in the deep-triode region to achieve a balanced temperature slope. The PMOS gate width was optimized to 50 µm in 180-nm CMOS to balance the CTAT/PTAT components. In addition, a body-effect (VSB) bias generator is employed to adjust the effective PMOS threshold voltage and further flatten the composite temperature characteristics. The reference is programmable trimmed by a two-stage coarse-fine decoder to realize a 3.2-4.2 V output range with 1 mV resolution, targeting ∆Σ ADC-based BMS front ends. The proposed design achieved an ultra-low temperature variation of 0.3 mV from -20℃ to 100℃, corresponding to a temperature coefficient of 0.61 ppm/◦C, with an active area of 0.0038 mm².