A Layered Strategy for Placement and Routing in Large-Scale Field-Coupled Nanocomputing Circuits

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Field-Coupled Nanocomputing (FCN) devices are emerging nanotechnologies for next-generation logic computing, driven by the physical limitations of CMOS technology. As the scale of circuit design increases, automatic placement and routing (P&R) become crucial for optimizing device performance and ensuring scalable fabrication. Previous algorithms face challenges in solving large-scale placement and routing problems with the current clocking scheme. In this article, a novel approach is proposed to decouple the placement and routing issues in the design of FCN logic circuits. By adopting a layered method, the issues are confined within each layer, and long wires between layers are eliminated while reducing crossovers through node sorting. A* algorithm is employed to solve the routing between logic gates, and an innovative clock allocation mechanism ensures clock synchronization. A standard cell library is used to implement the mapping of an FCN circuit from a gate-level layout to a nanocell-level layout. The proposed method demonstrates superior performance compared with state-of-the-art approaches such as fiction, Ropper, and genetic algorithms (GA). Specifically, it achieves higher success rates, fewer gates and faster execution times, along with lower delays–while also delivering reduced area overhead, particularly when compared with Ropper and GA. Furthermore, this article achieves automatic placement and routing of FCN circuits with over 1000 nodes, making it more suitable for large-scale FCN circuit design.