Design of a multilayer full adder/subtractor circuit in quantum-dot cellular automata technology

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Abstract Quantum-dot Cellular Automata (QCA) technology has emerged as an attractive post-CMOS nanotechnology that enables highly compact circuit implementations with high operating speed and low energy consumption. This paper introduces a new multilayer reversible full adder/subtractor architecture implemented in QCA technology. The presented architecture has a three-layer routing strategy together with reversibility concepts to minimize information loss and improve energy efficiency. The implementation relies on the basic QCA building blocks, namely majority, inverter, and XOR gates, where the XOR structure is responsible for generating the Sum/Difference output. The proposed reversible design produces only one garbage output to maintain the required one-to-one input–output mapping. The proposed design was implemented and verified using QCADesigner tool version 2.0.3. Simulation results confirm that the developed architecture requires only 91 QCA cells, achieves a delay of 1 clock cycle, and occupies an area of 0.06 μm 2 . The total energy dissipation of the circuit is $$4.36 \times {10}^{-2}$$ eV. Comparative evaluation against recently published QCA designs confirms that the proposed architecture offers a favorable trade-off between cell count, area, delay, and energy consumption for low-power reversible arithmetic units.